1. Field of the Invention
The present invention relates to a USB (Universal Serial Bus) interface circuit which has an OTG (On-The-Go) capability, and particularly to technologies for reducing the power consumption of the circuit.
2. Description of the Related Art
The USB OTG capability allows peripheral devices to perform serial data transmissions on a one-to-one basis with each other without the need of a host computer that was required in conventional USB specifications.
Two peripheral devices which have the USB OTG capability are connected via a cable with four signal lines: D+, D−, VBUS, and GND for mutually transmitting data to each other. The plugs at the ends of the cable are further provided with an ID terminal, with the ID terminal in one plug connected to the GND signal, and the ID terminal in the other plug unconnected. Each peripheral device operates so that, if the ID terminal of the inserted plug is connected to the GND signal, that peripheral device operates as the master, and if the ID terminal is unconnected, the device operates as the slave.
With the USB OTG capability, the signal VBUS is utilized to enable lower power consumption of the peripheral devices. More particularly, the peripheral device established as the master drives the signal VBUS at a “H” level during the period in which a data transmission is performed between the peripheral devices using the D+ and D− signals, and changes the signal VBUS to an “L” level when transmission is not required. Consequently, because there is no requirement to execute a transmission when the signal VBUS is “L”, a large proportion of the logic circuits concerned with transmission functions can be stopped, thus enabling a transition to a low power consumption mode.
However, even in the low power consumption mode, it is necessary to have a detection circuit running that detects changes in the signal ID and the signal VBUS, and to restart transmission functions and logic circuits such as those for master/slave switchover when a change in these signals is detected.
A USB interface circuit that has a conventional OTG capability is configured so that a clock signal generated by a master oscillator is frequency-divided by a divider circuit to generate a low-frequency clock, and change in the signal ID and signal VBUS is periodically detected based on the low-frequency clock. And when a change in the signal is detected, the master oscillator clock signal is supplied to the logic circuits so that they come out of the low power consumption mode. It should be noted that, although not regarding USB interface circuits, systems that use the same configuration for switching between a low power consumption mode and a normal operation mode are disclosed in, for example, Japanese Patent Application Kokai No.2001-211276 and No.2002-152439.
However, USB interface circuits with conventional OTG capability have the following problems.
It is necessary to have a master oscillator and a frequency divider constantly running in order to detect a signal change. According to USB specifications, the clock signal of a master oscillator is defined to be a frequency of 48 MHz with a precision of 500 ppm. Therefore, the power consumption of the master oscillator itself is large and the power consumption of the frequency divider that divides the clock signal is also large, thus posing a limitation to efforts at reducing power consumption.